Kalomiros, JohnLygouras, John2015-06-162024-09-272015-06-162024-09-272011-07http://www.sciencedirect.com/science/article/pii/S0141933111000603?np=y#https://repository2024.ihu.gr/handle/123456789/1305A new real-time stereo system is presented based on a hardware implementation of an efficient Dynamic Programming algorithm. A simple state-machine calculates the cost-matrix along the diagonal of the 2-D disparity space for each epipolar pair of image scan-lines. Minimum transition costs are stored in embedded RAM and are used to backtrack disparities at clock rate. All calculations are within a pre-determined slice of the cost plane, representing the useful disparity range. The system is designed as a VHDL library component and is implemented as a SoC in a medium-capacity Field Programmable Gate Array chip. It can process stereo-pairs in full VGA resolution at a rate of 25 Mpixels/s and produces 8-bit dense disparity maps within a range of disparities up to 65 pixels. The design is evaluated comparing to ground truth and in terms of resource usage. It is also compared to a software implementation of the Dynamic Programming algorithm and to other FPGA-based stereo systems.14enAttribution-NonCommercial-NoDerivatives 4.0 Διεθνέςhttp://creativecommons.org/licenses/by-nc-nd/4.0/Άρθρο σε επιστημονικό περιοδικό10.1016/j.micpro.2011.04.005Hardware designReal-time systemsStereo visionDynamic programming