Kalomiros, J. A.Lygouras, J.2015-06-252024-09-272015-06-252024-09-272008-030141-9331http://www.sciencedirect.com/science/article/pii/S014193310700110Xhttps://repository2024.ihu.gr/handle/123456789/1500We evaluate the performance of a hardware/software architecture designed to perform a wide range of fast image processing tasks. The system architecture is based on hardware featuring a Field Programmable Gate Array (FPGA) co-processor and a host computer. A LabVIEW™ host application controlling a frame grabber and an industrial camera is used to capture and exchange video data with the hardware co-processor via a high speed USB2.0 channel, implemented with a standard macrocell. The FPGA accelerator is based on a Altera Cyclone II chip and is designed as a system-on-a-programmable-chip (SOPC) with the help of an embedded Nios II software processor. The SOPC system integrates the CPU, external and on chip memory, the communication channel and typical image filters appropriate for the evaluation of the system performance. Measured transfer rates over the communication channel and processing times for the implemented hardware/software logic are presented for various frame sizes. A comparison with other solutions is given and a range of applications is also discussed.12enAttribution-NonCommercial-NoDerivatives 4.0 Διεθνέςhttp://creativecommons.org/licenses/by-nc-nd/4.0/Άρθρο σε επιστημονικό περιοδικό10.1016/j.micpro.2007.09.001Hardware/software co-designImage processingFPGAEmbedded processor