Πλοήγηση ανά Συγγραφέα "Lygouras, J."
Τώρα δείχνει 1 - 3 από 3
- Αποτελέσματα ανά σελίδα
- Επιλογές ταξινόμησης
Τεκμήριο Design and evaluation of a hardware/software FPGA-based system for fast image processing(2008-03) Kalomiros, J. A.; Lygouras, J.We evaluate the performance of a hardware/software architecture designed to perform a wide range of fast image processing tasks. The system architecture is based on hardware featuring a Field Programmable Gate Array (FPGA) co-processor and a host computer. A LabVIEW™ host application controlling a frame grabber and an industrial camera is used to capture and exchange video data with the hardware co-processor via a high speed USB2.0 channel, implemented with a standard macrocell. The FPGA accelerator is based on a Altera Cyclone II chip and is designed as a system-on-a-programmable-chip (SOPC) with the help of an embedded Nios II software processor. The SOPC system integrates the CPU, external and on chip memory, the communication channel and typical image filters appropriate for the evaluation of the system performance. Measured transfer rates over the communication channel and processing times for the implemented hardware/software logic are presented for various frame sizes. A comparison with other solutions is given and a range of applications is also discussed.Τεκμήριο Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array(2008-09) Kalomiros, J. A.; Lygouras, J.The design of a hardware co-processor for stereo depth detection, based on a parallel implementation of the sum of absolute differences algorithm, is presented. Model-based designs are followed, and a parameterisable open source VHDL library component appropriate for integration within a system-on-a- programmable chip is created. We target a field programmable gate array board featuring external memory and other peripheral components and implement the control path with a Nios II embedded processor clocked at 100 MHz. The hardware co-processor produces dense 8-bit disparity maps of 320times240 pixels at a rate of 25 Mpixels/s and can expand the disparity range from 32 to 64 pixels with appropriate memory techniques. Essential resources can be as low as 16 000 logic elements, whereas by migrating to more complex devices the design can easily grow to support better results.Τεκμήριο Hardware principles for the design of a stereo-matching state machine based on dynamic programming(2008) Kalomiros, J. A.; Lygouras, J.This paper presents basic design principles for hardware implementation of a two-pass stereo-matching algorithm based on dynamic programming. For the first-pass a state-machine is proposed for the recursive calculation of the cost-function. The state-machine works along the diagonal of a 2-D disparity space for each epipolar pair of image scan-lines. On-chip local RAM stores tags that denote the minimum transition cost to every point in the disparity space among possible costs from all three neighboring points. All calculations are within a pre-determined useful disparity range. For the second pass, hardware rules are presented that produce the correct disparity per pixel, by backtracking stored cost values. Hardware stages are structured along a fully parallel pipeline, that outputs disparities in step with the input serial pixel stream at clock rate.