Design and Implementation of a Hardware Accelerator for one-Dimensional signal Filtering Operations

Abstract

The objective of this thesis is the design of a low-pass Finite Impulse Response filter using hardware description language for FPGA implementation. The window design method was followed and the filter was described in VHDL. The design tool used for the synthesis of the filter is Quartus II v. 9.1 by Altera. Modelsim by Mentor Graphics was used for simulation, in order to verify the filter operation and the accuracy of the results. The comparison with a software-based implementation of the same filter demonstrates that the filter meets the requirements. Bottom-up hierarchical design was used. The various components were first described in VHDL and then they were instantiated in order to produce the top design entity of the filter. Such filter components that need description are the shift register for the creation of the convolution window, the ROM stage where the filter coefficients are stored, the computationally demanding parallel multiplication stage and finally, the accumulation and normalization stage, where the output sample is computed. Specifications for the necessary data types were defined and alternative implementations of specific stages were tested, as a means to establish best design methodology. We find that a filter with 101 coefficients can reproduce the original double precision filter specifications using just 14% of the resources of a Cyclone II EP2C35 low cost FPGA device. Also, it can achieve a maximum clock frequency of 50 MHz.