Σχεδίαση και μοντελοποίηση συνεπεξεργαστή στερεοσκοπικής όρασης και υλοποίηση σε FPGA

Abstract

We present the design of a hardware co-processor for stereo depth detection, based on a parallel implementation of the Sum of Absolute Differences algorithm. We follow model-based design and create a parametrizable open source VHDL library component appropriate for integration within a System-On-a- Programmable Chip (SOPC). We target a Field Programmable Gate Array (FPGA) board featuring external memory and other peripheral components and implement the control path with a Nios II embedded processor clocked at 100MHz. The hardware co-processor produces dense 8-bit disparity maps of 320x240 pixels at a rate of 25 Mpixels/sec and can expand the disparity range from 32 to 64 pixels with appropriate memory techniques. Essential resources can be as low as 16000 Logic Elements, while by migrating to more complex devices the design can easily grow to support better results.