Αποτελέσματα Ερευνητικών Προγραμμάτων
Μόνιμο URI για αυτήν τη συλλογήhttps://repository2024.ihu.gr/handle/123456789/30487
Δημοσιεύσεις που έχουν προκύψει από ερευνητικά προγράμματα που εκπονήθηκαν μέσω του ΤΕΙ Κεντρικής Μακεδονίας
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Τεκμήριο Design of FPGA-based image acquisition system for Advanced robotic applications(ΤΕΙ Κεντρικής Μακεδονίας, 2012) Καλόμοιρος, ΙωάννηςThe hardware/software implementation of a novel image acquisition system, designed to host advanced processing techniques, is introduced. The system is suitable for robotic vision applications, such as stereo image processing, visual odometry etc. The architecture is based on a Cyclone IV Altera FPGA device that constitutes the main processing unit and on a 32–bit Microchip PIC32 microcontroller as a complementary processor. The microcontroller undertakes peripheral control tasks, relieving valuable resources from the FPGA. The system can capture image data simultaneously from two CMOS sensors and store necessary image rows in FPGA's on chip memory. Moreover, it uses a FIFO-to-USB module to transfer plain or processed image data to a host computer. The system also supports VGA connectivity. Operational tasks such as frame grabbing, image processing and communication with high-speed USB module are implemented in VHDL. A host computer interface has also been developed in order to test the overall system in action. The system is evaluated in terms of real-time performance and the advantages emanating from the proposed architecture are discussed.Τεκμήριο Σχεδίαση και μοντελοποίηση συνεπεξεργαστή στερεοσκοπικής όρασης και υλοποίηση σε FPGA(Τ.Ε.Ι. Κεντρικής Μακεδονίας, 2008) Καλόμοιρος, ΙωάννηςWe present the design of a hardware co-processor for stereo depth detection, based on a parallel implementation of the Sum of Absolute Differences algorithm. We follow model-based design and create a parametrizable open source VHDL library component appropriate for integration within a System-On-a- Programmable Chip (SOPC). We target a Field Programmable Gate Array (FPGA) board featuring external memory and other peripheral components and implement the control path with a Nios II embedded processor clocked at 100MHz. The hardware co-processor produces dense 8-bit disparity maps of 320x240 pixels at a rate of 25 Mpixels/sec and can expand the disparity range from 32 to 64 pixels with appropriate memory techniques. Essential resources can be as low as 16000 Logic Elements, while by migrating to more complex devices the design can easily grow to support better results.Τεκμήριο Μελέτη μεθόδων στερεοσκοπικής επεξεργασίας με χρήση εξειδικευμένου υλικού(Τ.Ε.Ι. Κεντρικής Μακεδονίας, 2008) Καλόμοιρος, ΙωάννηςThe processing results of two stereo accelerators implemented in reconfigurable hardware are presented. The first system implements a local method to find correspondences, the sum of absolute differences, while the second uses a global approach based on dynamic programming. The basic design principles of the two systems are presented and the systems are tested using a multitude of reference test benches. The resulting disparity maps are compared in terms of rms error and percentage of bad matches, using both textured and textureless image areas. A stereo head is developed and used with the accelerators, testing their ability in a real-world experiment of map reconstruction in real-time. It is shown that the DP-based accelerator produces the best results in almost all cases and has advantages over traditional hardware implementations based on local SAD correlation.